Peripheral operating requirements and behaviors6.6.3.2SymbolP12-bit DAC operating behaviorsDescriptionMin.——————VDACR−100—————60———1.20.05—55040Table 33.12-bit DAC operating behaviorsTyp.——100150.7—————±0.4±0.1—3.70.000421—1.70.12———Max.3301200200301100VDACR±8±1±1±0.8±0.690——250——-80——dBkHzUnitμAμAμsμsμsmVmVLSBLSBLSB%FSR%FSRdBμV/C%FSR/CΩV/μs623455111NotesIDDA_DACLSupply current — low-power modeIDDA_DACHSupply current — high-speed modePtDACLPtDACHPFull-scale settling time (0x080 to 0xF7F) —low-power modeFull-scale settling time (0x080 to 0xF7F) —high-power modetCCDACLPCode-to-code settling time (0xBF8 to 0xC08)— low-power mode and high-speed modeVdacoutlVdacouthINLDNLDNLDAC output voltage range low — high-speedmode, no load, DAC set to 0x000DAC output voltage range high — high-speed mode, no load, DAC set to 0xFFFIntegral non-linearity error — high speedmodeDifferential non-linearity error — VDACR > 2VDifferential non-linearity error — VDACR =VREF_OUTGain errorPower supply rejection ratio, VDDA > = 2.4 VTemperature coefficient offset voltageTemperature coefficient gain errorOutput resistance load = 3 kΩSlew rate -80h→ F7Fh→ 80h•High power (SPHP)•Low power (SPLP)CTBWChannel to channel cross talk3dB bandwidth•High power (SPHP)•Low power (SPLP)VOFFSETOffset errorEGPSRRTCOTGERopSR1.2.3.4.5.6.
Settling within ±1 LSB
The INL is measured for 0+100mV to VDACR−100 mVThe DNL is measured for 0+100 mV to VDACR−100 mV
The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4VCalculated by a best fit curve from VSS+100 mV to VDACR−100 mV
VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC setto 0x800, Temp range from -40C to 105C
K20 Sub-Family Data Sheet, Rev. 3, 6/2013.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviorsTable 35.VREF full-range operating behaviorsSymbolVoutVoutVoutVstepVtdriftIbgIlpIhpΔVLOADDescriptionVoltage reference output with factory trim atnominal VDDA and temperature=25CVoltage reference output — factory trimVoltage reference output — user trimVoltage reference trim stepTemperature drift (Vmax -Vmin across the fulltemperature range)Bandgap only currentLow-power buffer currentHigh-power buffer currentLoad regulation•current = ± 1.0 mATstupVvdriftBuffer startup timeVoltage drift (Vmax -Vmin across the full voltagerange)———200—2—100—µsmV1Min.1.19151.15841.193—————Typ.1.195——0.5————Max.1.19771.23761.197—80803601UnitVVVmVmVµAuAmAµV1111, 2Notes1.See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2.Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 36.VREF limited-range operating requirementsSymbolTADescriptionTemperatureMin.0Max.50Unit°CNotesTable 37.VREF limited-range operating behaviorsSymbolVoutDescriptionVoltage reference output with factory trimMin.1.173Max.1.225UnitVNotes6.7Timers
See General switching specifications.
6.8Communication interfaces
K20 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc.
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