元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004INTERLEAVED DUAL PWM CONTROLLER WITH PROGRAMMABLE MAX DUTY CYCLEFEATURESD2-MHz High Frequency Oscillator with 1-MHzDDDDDDDDDAPPLICATIONSDHigh Output Current (50-A to 100-A)DDDOperation Per ChannelMatched Internal Slope CompensationCircuitsProgrammable Maximum Duty Cycle Clamp60% to 90% Per ChannelPeak Current Mode Control withCycle-by-Cycle Current LimitCurrent Sense Discharge Transistor forImproved Noise ImmunityAccurate Line Under and Over-Voltage Sensewith Programmable HysteresisOpto-Coupler Interface110-V Internal Start-Up JFET (UCC28221)Operates from 12-V Supply (UCC28220)Programmable Soft-StartConvertersMaximum Power Density DesignsHigh Efficiency 48-V Input with Low OutputRipple ConvertersHigh Power Offline, Telecom and DatacomPower SuppliesDESCRIPTIONThe UCC28220 and UCC28221 are a family of BiCMOSinterleaved dual channel PWM controllers. Peakcurrent mode control is used to ensure current sharingbetween the two channels. A precise maximum dutycycle clamp can be set to any value between 60% and90% duty cycle per channel.UCC28220 has an UVLO turn-on threshold of 10 V foruse in 12-V supplies while UCC28221 has a turn-onthreshold of 13 V for systems needing wider UVLOhysteresis. Both have 8-V turn-off thresholds.TYPICAL APPLICATIONVIN(+48V)CS1UCC282211LINEOVVIN162LINEHYS3VDD4CS15SLOPE6CS27SSLINEUV15REF141/2 UCC27324OUT113OUT212GND11CHG10REF1/2 UCC27324E/AVOUTBiasCS28CTRLDISCHG9NOTE:Pin 16 is a no connect (N/C) on UCC28220 which does not include the JFET option.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright 2004, Texas Instruments Incorporatedwww.ti.com1元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004DESCRIPTION (CONTINUED)Additional features include a programmable internal slope compensation with a special circuit which is used toensure exactly the same slope is added to each channel and a high voltage 110-V internal JFET for easierstartup for the wider hysteresis UCC28221 version.The UCC28220 is available in both 16-pin SOIC and low-profile TSSOP packages. The UCC28221 also comesin 16-pin SOIC package and a slightly larger 20-pin TSSOP package to allow for high voltage pin spacing tomeet UL1950 creepage clearance safety requirements.ORDERING INFORMATIONTEMPERATURE RANGE TA = TJ−40°C to +105°CUVLO THRESHOLDS10 V on / 8 V off13 V on / 8 V off110-V HV JFETSTARTUP CIR-CUITNOYESPACKAGED DEVICESSOIC−16 (D)UCC28220DUCC28221DTSSOP-16 (PW)UCC28220PW−TSSOP-20 (PW)−UCC28221PWNOTE:D (SOIC) and PW (TSSOP) packages are available taped and reeled. Add R suffix to device type, e.g. UCC28220DR or UCC28221PWR.The reel quanities are 2,500 devices per reel for D package and 2,000 devices per reel for the PW package.CONNECTION DIAGRAMUCC28220D, UCC28220PWand UCC28221D PACKAGE(TOP VIEW)UCC28221PW PACKAGE(TOP VIEW)LINEOVLINEHYSVDDCS1SLOPECS2SSCTRL1234 5678161514131211109VIN (for UCC28221)N/C (for UCC28220)LINEUVREFOUT1OUT2GNDCHGDISCHGN/CLINEOVLINEHYSVDDCS1SLOPECS2SSCTRLN/C1234 5671020191817161514131211VINN/CLINEUVREFOUT1OUT2GNDCHGDISCHGN/CRECOMMENDED OPERATION CONDITIONSParameterHigh voltage start-up inputSupply voltageSymbolVINVDDCondition36 V to 76 V8 V to 14.5 V2www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted)†}ParameterHigh voltage start-up input, VINSupply voltage, VDDOutput current (OUT1, OUT2) dc , IOUT(dc)OUT1/ OUT2 capacitive loadREF output current, IREFCurrent sense inputs, CS1, CS2Analog inputs (CHG, DISCHG, SLOPE, REF, CNTRL)Analog inputs (SS, LINEOV, LINEUV, LINEHYS)Power dissipation at TA = 25°C (PW package)Power dissipation at TA = 25°C (D package)Junction operating temperature, TJStorage temperature, TstgLead temperature (soldering, 10 sec.), TsolUCC2822X11015±1020010−1.0 to 2.0−0.3 to 3.6−0.3 to 7.0400650−55 to 150−65 to 150300UNITVVmApFmAVVVmWmW°C°C°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute−maximum−rated conditions for extended periods may affect device reliability.‡All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databookfor thermal limitations and considerations of packages.ELECTRICAL CHARACTERISTICS:VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = −40°C to105°C, TA = TJ, (unless otherwise noted).PARAMETEROverall SectionOperating VDD rangeQuiescent currentOperating currentStartup SectionStartup currentStartup currentUVLO start thresholdUVLO start thresholdUVLO stop thresholdUVLO hysteresisUVLO hysteresisJFET ON thresholdJFET ON thresholdHigh voltage JFET currentHigh voltage JFET currentHigh voltage JFET currentJFET leakageUCC28220 VDD < (UVLO−0.8)UCC28221 VDD < (UVLO−0.8)UCC28220UCC28221 UCC28220UCC28221SS = 0, outputs not switching, VDD decreasingSS = 2 V,Cntrl = 2 V, output switching, VDD decreasing; same threshold as UVLO stopVIN = 36 V to 76 V, VDD = 0 VVIN = 36 V to 76 V, VDD = 10 VVIN = 36 V to 76 V, VDD < UVLOVIN = 36 V to 76 V, VDD = 14 V 9.512.37.61.84..57.614 1013825108481612 20050010.513.78.42.25.210.58.41004040100µAmAVVVµA SS = 0 V, no switching, Fosc = 1 MHzOutputs switching, Fosc = 1 MHz81.51.6 33.51446VmATEST CONDITIONMINTYPMAXUNITSwww.ti.com3元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004ELECTRICAL CHARACTERISTICS:VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = −40°C to105°C, TA = TJ, (unless otherwise noted).PARAMETERReferenceOutput voltageOutput currentOuput short circuit currentVREF UVLOSoft-StartSS charge currentSS discharge currentSS initial voltageSS voltage at 0% dcSS voltage ratioSS Max voltageOscillator and PWMOutput frequencyOscillator frequencyOutput maximum duty cycleCHG voltageDISCHG voltageSlope CompensationSlopeChannel matchingCurrent SenseCS1, CS2 bias currentProp delay CSx to OUTxCS1, CS2 sink currentCNTRL SectionResistor ratio(1)Ctrl input currentCtrl voltage at 0% dcCTRL = 0 V and 3.3 VCSx = 0 V, Point at which output starts switching (checksresistor ratio)CS1 = 0, CS2 = 0CSx input 0 V to 1.5 V stepCSx = 2 V−500 2.3 −1000.50404.50.601.2500857 1001.8nAnsmA nAVRSLOPE = 75 kΩ, RCH = 66 kΩ, RDISCHG = 44 kΩ, Csx =0 V to 0.5 VRSLOPE = 75 kΩ, Csx = 0 V140 200 0%26010%mV/usRCHG = 10.2 kΩ, RDISCHG = 10.2 kΩRCHG = 10.2 kΩ, RDISCHG = 10.2 kΩRCHG = 10.2 kΩ, RDISCHG = 10.2 kΩ, measured at OUT1and OUT2 45090073%22500100075%2.52.5550110077%33kHz%V8 V < VDD < 14 V, ILOAD=0 mA to −10 mAOutputs not switching; CNTRL = 0 VVREF = 0 V RCHG=10.2 kΩ, SS = 0 VRCHG=10.2 kΩ, SS = 2 VLINEOV=2 V, LINEUV = 0 VPoint at which output starts switching LINEOV = 0 V, LINEUV = 2 V3.1510−402.55−70700.50.575%33.3 −203−10010011.290%3.53.45 −103.25−1301301.51.8100%4VVmAmAVTEST CONDITIONMINTYPMAXUNITSµAVNOTES:(1).Ensured by design. Not 100% tested in production.4www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004ELECTRICAL CHARACTERISTICS:VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = −40°C to105°C, TA = TJ, (unless otherwise noted).PARAMETEROutput Section (OUT1, OUT2)Low levelHigh levelRise timeFall timeLINE Sense sectionLINEOV thresholdLINEOV thresholdLINEUV thresholdLINEUV thresholdLINEHYST pull up voltageLINEHYST off leakageLINEHYS pull-up resistanceLINEHYS pull-down resistanceLINEOV, LINEUV bias ITA = 25°CTA =−40°C to 105°CTA = 25°CTA =−40°C to 105°CLINEOV = 2 V, LINEUV = 2 VLINEOV = 0 V, LINEUV = 2 VI = −20 µAI = 20 µALINEOV = 1.25 V, LINEUV = 1.25 V1.2401.2351.2401.2353.1−500 −5001.2601.2601.2601.2603.250100100 1.2801.2851.2801.2853.4500500500500nAΩnAVIOUT = 10 mAIOUT = −10 mA, VREF – VOUTCLOAD = 50 pFCLOAD = 50 pF 0.40.41010112020VnsTEST CONDITIONMINTYPMAXUNITSNOTES:(1).Ensured by design. Not 100% tested in production.www.ti.com5元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004FUNCTIONAL BLOCK DIAGRAMREF14REFERENCERUNUVLO/ JFETCONTROLP2CHG10OSCDISCHG9TQFFQ++RUNSLOPECOMPENSATIONCS260.5 V++RUNSLOPECTRL58++−20 kΩCLK2SQLATCHRQVREFCLK1CLK2CLK1SQLATCHRQVREF16VIN(N/C onUCC28220)3VDDCS140.5 V13OUT111GND12OUT21LINEOV30 kΩ1 pFLINE OV/UV2LINEHYS15LINEUVSoft−StartSS7RUNNOTE:Pinout for 16 pin option shown. See the 20-pin connection to UCC28221PW in the Terminal Functions table on the next page.6www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004Terminal FunctionsTERMINALPIN NUMBERUCC28220DUCC28220PW1234567101112131415−16UCC28221D123456710111213141516−UCC28221PW23456712131415161718201, 10, 11, 19NAMELINEOVLINEHYSVDDCS1SLOPECS2SSCTRLDISCHGCHGGNDOUT2OUT1REFLINEUVVINN/CI/OIIIIIIIIII−OOOII−FUNCTIONInput for line over voltage comparatorSets line comparator hysteresisDevice supply inputChannel 1 current sense inputSets slope compensationChannel 2 current sense inputSoft-start inputFeedback control inputSets oscillator discharge currentSets oscillator charge currentDevice groundPWM output from channel 2PWM output from channel 1Reference voltage outputInput for line under voltage comparatorHigh voltage start-up inputNo connectionPIN DESCRIPTIONSVDD: This is used to supply power to the device, monitoring this pin is a the UVLO circuit. This is used to insureglitch-free startup operation. Until VDD reaches its UVLO threshold, it remains in a low power mode, drawingapproximately 150 µA of current and forcing pins, SS, CS1, CS2, OUT1, and OUT2 to logic 0 states. If the VDDfalls below 8 V after reaching turn-on, it will go back into this low power state. In the case of the UCC28221, theUVLO threshold is 13 V. It is 10 V for the UCC28220. Both versions have a turn-off threshold of 8 V.VIN (UCC28221 only): This pin has an internal high voltage JFET used for startup. The drain is connected toVIN, while its’ source is connected to VDD. During startup, this JFET delivers 12 mA typically with a minimumof 4 mA to VDD, which in turn, charges up the VDD bypass capacitor. When VDD gets to 13 V, the JFET is turnedoff.CS1 and CS2: These 2 pins are the current sense inputs to the device. The signals are internally level shiftedby 0.5 V before the signal gets to the PWM comparator. Internally the slope compensation ramp is added to thissignal. The linear operating range on this input is 0 to 1.5 V. Also, this pin gets pulled to ground each time itsrespective output goes low. (ie: OUT1 and OUT2).SLOPE: This pin sets up a current used for the slope compensation ramp. A resistor to ground sets up a current,which is internally divided by 25 and then applied to an internal 10-pF capacitor. Under normal operation th dcvoltage on this pin is 2.5 V..SS: A capacitor to ground sets up the soft-start time for the open loop soft-start function. The source and sinkcurrent from this pin is equal to 3/7th of the oscillator charge current set by the resistor on the CHG pin. Thesoft start capacitor is held low during UVLO and during a Line OV or UV condition. Once an OV or UV faultoccurs, the soft-start capacitor is discharged by a current equal to its charging current. The capacitor does NOTquickly discharge during faults. In this way, the controller has the ability to recover quickly from very short linetransients. This pin can also be used as an Enable/Disable function.www.ti.com7元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004CHG: A resistor from this pin to GND sets up the charging current of the internal CT capacitor used in theoscillator. This resistor, in conjunction with the resistor on the DISCHG pin is used to set up the operatingfrequency and maximum duty cycle. Under normal operation the dc voltage on this pin is 2.5 V.DISCHG: A resistor from this pin to GND sets up the discharge current of the internal CT capacitor used in theoscillator. This resistor, in conjunction with the resistor on the CHG pin is used to set up the operating frequencyand maximum duty cycle. Under normal operation the dc voltage on this pin is 2.5 V.OUT1 and OUT2: These output buffers are intended to interface with high current MOSFET drivers. The outputdrive capability is approximately 33 mA and has an output impedance of 100 Ω. The outputs swing betweenGND and REF.LINEOV: This pin is connected to a comparator and used to monitor the line voltage for an over voltagecondition. The typical threshold is 1.26 V.LINEUV: This pin is connected to a comparator and used to monitor the line voltage for an under voltagecondition. The typical threshold is 1.26 V.LINEHYST: This pin is controlled by both the LINEOV and LINEUV pins. It is used to control the hysteresisvalues for both the over and under voltage line detectors.REF: REF is a 3.3-V output used primarily as a source for the output buffers and other internal circuits. It isprotected from accidental shorts to ground. For improved noise immunity it is recommended that the referencepin be bypassed with a minimum of 0.1 µF of capacitance to GND.APPLICATION INFORMATIONGeneralThe device is comprised of several housekeeping blocks as well as two slope compensated PWM channels thatare interleaved. The circuit is intended to run from an external VDD supply voltage between 8 V and 14 V,however, the UCC28221 has the addition of a high voltage startup JFET with control circuitry which can be usedfor system startup. Other functions contained in the device are supply UVLO, 3.3-V reference, accurate line OVand UV functions, a high speed programmable oscillator for both frequency and duty cycle, programmable slopecompensation, and programmable soft start functions.The UCC28220/1 is a primary side controller for a two channel interleaved power converter. The device iscompatible with forward or flyback converters as long as a duty cycle clamp between 60 and 90 percent isrequired. The active clamp forward and flyback converters as well as the RCD and resonant reset forwardconverters are therefore compatible with this device. To ensure the two channels share the total converter outputcurrent, current mode control with internal slope compensation is used. Slope compensation is userprogrammable via a dedicated pin and can be set over a 50:1 range, ensuring good small-signal stability overa wide range of applications.8www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004APPLICATION INFORMATIONLINE Over Voltage and Under VoltageThree pins are provided to turn-off the output drivers and reset the soft-start capacitor when the converter inputvoltage is outside a prescribed range. The under-voltage set point and under-voltage hysteresis are accuratelyset via external resistors. The over-voltage set point is also accurately set via a resistor ratio, but the hysteresisis fixed by the same resistor that sets the u*nder-voltage hysteresis.Figure 1 and 2 show detailed functional diagram and operation of the under voltage lockout (UVLO) andover-voltage lockout (OVLO) features. The equations for setting the thresholds defined in Figure 2 are:V1+1.26 V2+1.26 V4+1.26 R1)1.26(R2)R3)(R1)Rx),whereRx+R4Ŧ(R2)R3)Rx(R1)R2)R3)R3(1)(2)(3)(4)V3+V4*1.26 R1R4ǒǓThe UVLO hysteresis and the OVLO hysteresis can then be calculated as V2 − V1 and V4 − V3, respectively.By examining the design equations it becomes apparent that the value of R4 sets the amount of hysteresis atboth thresholds. By realizing this fact, the designer can then set the value of R4 based on the most criticalhysteresis specification either at high line or at low line. In most designs the value of R4 will be determined bythe desired amount of hysteresis around the UVLO threshold. As an example consider a telecom power supplywith the following input UVLO and OVLO design specifications:••••Then,V1 = 32.0 VV2 = 34.0 VV3 = 83.0 VV4 = 84.7 VR1 = 976 kΩR2 = 24.9 kΩR3 = 15.0 kΩR4 = 604 kΩ•••and•www.ti.com9元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004APPLICATION INFORMATIONInputVoltageR1UV151.26 V+S1OPENHYS2R4S2CLOSEDR2LINE_GOOD1.26 V+OVR311.26 V+Figure 1. Line UVLO and OVLO Functional DiagramENABLELINE_GOODOFFV1V2V3V4Figure 2. Line UVLO and OVLO OperationVDDBecause the driver output impedance is high the energy storage requirements on the VDD capacitor is low. Forimproved noise immunity it is recommended that the VDD pin, be bypassed with a minimum of 0.1 µF ofcapacitance to GND. In most typical applications the bias voltage for the MOSFET drivers will also be used asthe VDD supply voltage for the chip. In the aforementioned applications it is beneficial to add a low valuedresistor between the bulk storage capacitor of the driver and the VDD capacitor for the UCC28220/1. By addinga resistor in series with the bias supply any noise that is present on the bias supply will be filtered out beforegetting to the VDD pin of the controller.10www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004APPLICATION INFORMATIONReferenceFor improved noise immunity it is recommended that the reference pin, REF, be bypassed with a minimum of0.1uF of capacitance to GND.Oscillator Operation and Maximum Duty Cycle SetpointThe oscillator uses an internal capacitor to generate the time base for both PWM channels. The oscillator isprogrammable over a 200 kHz to 2MHz frequency range with 20% to 80% maximum duty cycle range. Both thedead time and the frequency of the oscillator are divided by 2 to generate the PWM clock and off-time informationfor each of the outputs. In this way, a 20% oscillator duty cycle corresponds to a 60% maximum duty cycle ateach output, where an 80% oscillator duty cycle yields a 90% duty cycle clamp at each output.The design equations for the oscillator and maximum duty cycle set point are given by:FOSC+2 FOUTDMAX(osc)+1*2 1*DMAX(out)RCHG+KOSC DMAX(osc)FOSC(7)(5)ǒǓ(6)RDISCHG+KOSC Where:ǒ1*DMAX(osc)ǓFOSC(8)•••••••KOSC = 2.04 x 1010 [Ω/s]FOUT = Switching frequency at the outputs of the chip [Hz]DMAX(out) = Maximum duty cycle limit at the outputs of the chipDMAX(osc) = Maximum duty cycle of the Oscillator for the desired maximum duty cycle at the outputsFOSC = Oscillator frequency for desired output frequency [Hz]RCHG = External oscillator resistor which sets the charge current − [Ω]RDISCHG = External oscillator resistor which sets the discharge current − [Ω]Start-Up JFET SectionA 110-V start-up JFET is included to start the device from a wide range (36 V−75 V) telecom input source. WhenVDD is lower than 13 V the JFET is on, behaving as a current source charging the bias capacitors on VDD andsupplying current to the device. In this way, the VDD bypass capacitors are charged to 13 V where the outputsstart switching and the JFET is turned off. To enable a constant bias supply to the device during a pulse skippingcondition, the JFET is turned back on whenever VDD decreases below 10 V and the outputs are not switching.Thus, the current from the JFET can overcome the internal bias currents, as long as the device is not activelyswitching the output drivers. See Figure 2 below for a graphical representation of the JFET/VDD operation. TheUCC28220 does not contain an internal JFET and has a startup threshold of 10 V which makes it capable ofdirectly operating off a 12 V dc buswww.ti.com11元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004APPLICATION INFORMATIONVDD13 V8 − 14 V10 VNORMAL OPERATION8 V (UVLO off)13 V0VOUTxGATE DRVOFFONHV JFETONOFFFigure 3. JFET Device Operation with VDD VoltageSoft-StartA current is forced out of the SS pin, equal to 3/7 of the current set by RCHG, to provide a controlled ramp voltage.The current set by the RCHG resistor is equal to 2.5 V divided by RCHG. This ramp voltage overrides thecommanded duty cycle on the CTRL pin, allowing a controlled start-up. Assuming the UCC28221 is biased onthe primary side, the soft start should be quite quick to allow the secondary bias to be generated and thesecondary side control can then take over. Once the soft-start time interval is complete, a closed loop soft-starton the secondary side can be executed.ISS+3 2.57RCHGwhere,ISS = current which is sourced out of the SS pin during the soft-start time − [Amps](9)Current SenseThe current sense signals CS1 and CS2 are level shifted by 0.5 V and have the slope compensation rampsadded to them before being compared to the control voltage at the input of the PMW comparators. Theamplitude of the current sense signal at full load should be selected such that it is very close to the maximumcontrol voltage in order to limit the peak output current during short circuit operation.Output DriversThe UCC28220/1 is intended to interface with the UCC27323/4/5 family of MOSFET drivers. As such, the outputdrive capability is low, effectively 100 Ω and the driver outputs swing between GND and REF.12www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004APPLICATION INFORMATIONSlope CompensationThe slope compensation circuit in the UCC28220/1 operates on a cycle-by-cycle basis. The two channels haveseparate slope compensation circuits. These are fabricated in precisely the same way so as current sharingis unaffected by the slope compensation circuit. For each channel, an internal capacitor is reset whenever thatchannel’s output is off. At the beginning of the PWM cycle, a current is mirrored off the SLOPE pin into thecapacitor, developing an independent ramp. Since the two channel’s ramps will start when the channel’s outputchanges from a low to high state, the ramps are thus interleaved. These internal ramps are added to the voltageson the current sense pins, CS1 and CS2 and the result forms an input to the PWM comparators.REF2.5/(25*R_SLOPE) = I_SCSLOPE(5)R_SLOPEPWM−TO RESETof PWM LATCH+0.5V+CTRL(8)C_SCOUT 1ON OFFS110 pFCS1(4)S2Figure 4. Slope Compensation Detail for Channel 1. Duplicate Matched Circuitry Exists for Channel 2.To ensure stability, the slope compensation circuit must add between 1/5 and 1 times the inductor downslopeto each of the current sense signals prior to being applied to the PWM comparator’s input.www.ti.com13元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004APPLICATION INFORMATIONDetermining the value for the slope compensation resistor:Design Example:NCT(p) = 1NCT(s) = 50VOUT = 12LOUT = 3.2 x 10 −6Np = 7Ns = 5RSENSE = 5.23VEA(cl) = 1.98FS(out) = 500000Where,•••••••••NCT(p) = Number of primary turns on the Current Transformer − [Turns]NCT(s) = Number of Secondary turns on the current transformer − [Turns]VOUT = Nominal output voltage of the converter − [V]LOUT = Inductance value of each output inductor − [H]NP = Number of primary turns on the main transformer − [Turns]NS = Number of secondary turns on the main transformer − [Turns]RSENSE = Value of current sense resistor on secondary of current sense transformer − [Ohms]VEA(cl) = Maximum Value of the E/A output voltage − [Volts]FS(out) = Switching frequency of each output − [Hz]Determine the correct value for the slope resistor, RSLOPE, to provide the desired amount of slopecompensation.NCT+NCT(p)NCT(s),CurrentTransformerTurnsRatio1.Transform the Secondary Inductor Downslope to the PrimaryVOUTNsSL(prime)+ ,LOUTNpSL(prime)+2.679Ańms2.Calculate the Transformed Slope Voltage at Sense Resistor:VSL(prime)+SL(prime) NCT RSENSE,VSL(prime)+2.281Vńms3.Calculate the RSLOPE value to give a compensating ramp equal to the transformed slope voltage givenabove.:M+1.0Desired ratio between the compensating ramp and the output inductor downslope ramp, transformed to theprimary sense resistorRSLOPE+ǒM VSL(prime) 10*6Ǔ104,RSLOPE+35.556kW14www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004TYPICAL APPLICATION CIRCUITSVINCS1UCC282211OVVIN162HYSBias3VDD4CS15SLOPE6CS27SS8CTRLREF141/2 UCC27424OUT113CS2OUT212GND11CHG10DISCHG9UV15VOUT1/2 UCC27424REFE/AFigure 5. Interleaved Flyback Application Circuit Using the UCC28221www.ti.com15元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004VINCS1UCC282201OVN/C162Bias3HYSVDDUV151/2 UCC27424REF1445CS1SLOPEOUT113OUT212CS2VOUT67CS2SSGND11CHG101/2 UCC274248CTRLDISCHG9E/AFigure 6. Interleaved Boost Application Circuit Using the UCC2822016www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004TYPICAL CHARACTERISTICSUVLO THRESHOLDSvsTEMPERATURE4.013.5VUVLO − UVLO Thresholds− VUCC28221 UVLO on thresholdIDD − Quiescent Current − mA3.53.02.52.01.51.00.50.0−50−2502550751001250246810121416VDD − Supply Voltage − VQUIESCENT CURRENTvsSUPPLY VOLTAGEUCC28221 EXCLUDES JFET CURRENT12.511.5UCC28220 UVLO on threshold and UCC28221JFET on threshold (when not switching)9.5UCC28220 and UCC28221 UVLO off threshold and UCC28221 JFET on threshold (when switching)8.57.5Tj − Temperature − °CFigure 7SUPPLY CURRENTvsSUPPLY VOLTAGE3020IDD − Supply Current − mA100−10−20−30−40−500246810121416VDD − Supply Voltage − V3.45Figure 8REFERENCE VOLTAGEvsTEMPERATUREVIN = 36 VVREF − ReferenceVoltage − V3.40UCC282213.353.30No Load3.25Load3.20JFET source current3.15−50−250255075100125Tj − Temperature − °CFigure 9Figure 10UCC28220UCC282211710.5www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004TYPICAL CHARACTERISTICSLINEOV AND LINEUV THRESHOLDSvsTEMPERATURE1.2701.265SLOPE − Slope Compensation − mV per µs1.260Vth − Trip Threshold − V1.2551.2501.2451.2401.2351.230−50−250255075100125Tj − Temperature − °C230225SLOPE COMPENSATIONvsTEMPERATURERSLOPE = 75 kΩLINEOV220215210205200195190185180175170−50−250.0255075100125Tj − Temperature − °CCS1 = 0 VLINEUVCS1 = 0.5 VFigure 11PROGRAMMING RESISTORvsSLOPE COMPENSATION106RSLOPE − Slope Programming Resistor − ΩFigure 12CHANNEL1 AND CHANNEL2 SLOPE MATCHINGvsTEMPERATURE108Mismatch − %10520−2−4−6−8RSLOPE = 75 kΩCS0 = 0 VCS1 = 0 V10410310100SLOPE − Slope Compensation − mV per µs1000−10−50−250.0255075100125Tj − Temperature − °CFigure 13Figure 1418www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004TYPICAL CHARACTERISTICSRISE AND FALL TIMEvsTEMPERATURE (CL = 50 pf)20191817Tr and Tf − Rise and Fall Time − ns161514131211109876543210−501.00.90.8VO -Output Voltage − VVOH AND VOLvsTEMPERATUREIOUT = 10 mAFall Time0.70.60.50.4VREF − VOUT (VOH)Rise TimeVOL0.30.20.1−2502550751001250.0−50−250255075Tj − Temperature − °C100125Tj − Temperature − °CFigure 15SOFTSTART CHARGE CURRENTvsTEMPERATURE−70130Figure 16SOFTSTART DISCHARGE CURRENTvsTEMPERATURERCHG = 10.2 kΩISSCH − Charge Current − µAISSdis − Charge Current − µA−80120−90110−100100−11090−12080−130−50−250255075100125Tj − Temperature − °C70−50−250255075100125Tj − Temperature − °CFigure 17Figure 18www.ti.com19元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004TYPICAL CHARACTERISTICSPROGRAMMING RESISTORSvsSWITCHING FREQUENCY1M550540RCHRG RDISRG − Resistance − ΩOSCILLATOR FREQUENCYvsTEMPERATURERCHRG = RDISRG = 10.2 kΩfS - Oscillator Frequency − kHz10M100KRCHRG = RDISRGDMAX = 75%53052051050049048047046045010K1K10K100K1MfS - Switching Frequency − Hz−50−250255075100125Tj − Temperature − °CFigure 19PROGRAMMABLE MAX DUTY CYCLEvsTEMPERATURE7710090807060504030201073−50−250255075100125Tj − Temperature − °C000.2Figure 20CSx to OUTx delayvsCSx Peak VoltageRCHRG = RDISRG = 10.2 kΩ76DC − Duty Cycle − %CSx to OUTx delay − ns105°C25°C−40°C75740.40.60.81.01.2CSx − Peak Voltage − V1.41.61.8Figure 21Figure 2220www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004APPLICATION INFORMATIONRelated ProductsDEVICEUCC27323/4/5UCC27423/4/5TPS2811/12/13UC3714/15DESCRIPTIONDual 4-A High Speed Low Side MOSFET DriversDual 4-A High Speed Low Side MOSFET Driverswith EnableDual 2.4-A High Speed Low Side MOSFET DriversDual 2.4-A High Speed Low Side MOSFET DriversPACKAGE OPTIONSOIC-8, PowerPAD MSOP-8, PDIP-8SOIC-8, PowerPAD MSOP-8, PDIP-8SOIC-8, TSSOP-8, PDIP-8SOIC-8, PowerSOIC-14, PDIP-8References and Resources:An evaluation module and an associated user’s guide are available. The UCC28221 is used in a two-channelinterleaved Forward design converting from 36-V to 76-V dc input voltage to a regulated 12-V dc output. Thepower module has two isolated 100 W forward power stages operating at 500 kHz, which are operating 180degrees out of phase with each other allowing for output current ripple cancellation and smaller magneticdesign. This design also takes advantage of the UCC28221’s on-board 110-V internal JFET start up circuit thatremoves the need of an external trickle charge resistor for boot strapping. This circuit turns off after auxiliarypower is supplied to the device conserving power.DEvaluation Module, UCC28221EVM, 48 VIN, 12 VOUT, 200-W Interleaved Forward ConverterDUser’s Guide, UCC28221 Evaluation Module, Texas Instruments Literature Number SLUU173www.ti.com21元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004MECHANICAL DATAD (R-PDSO-G**) PACKAGE8 PINS SHOWN0.050 (1,27)850.020 (0,51)0.014 (0,35)0.010 (0,25)PLASTIC SMALL-OUTLINE0.244 (6,20)0.228 (5,80)0.157 (4,00)0.150 (3,81)0.008 (0,20) NOMGage Plane1A40°− 8°0.044 (1,12)0.016 (0,40)0.010 (0,25)Seating Plane0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)0.004 (0,10)PINS **DIMA MAXA MIN80.197(5,00)0.1(4,80)140.344(8,75)0.337(8,55)160.394(10,00)0.386(9,80)4040047/E 09/01NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Body dimensions do not include mold flash orprotrusion, not to exceed 0.006 (0,15).D.Falls within JEDEC MS-01222www.ti.com元器件交易网www.cecb2b.comUCC28220, UCC28221SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004MECHANICAL DATAPW (R-PDSO-G**) PACKAGE14 PINS SHOWNPLASTIC SMALL-OUTLINE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°−8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,902,80A MIN2,904,904,906,407,709,6040400/F 01/97NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Body dimensions do not include mold flash orprotrusion not to exceed 0,15.D.Falls within JEDEC MO-153www.ti.com23元器件交易网www.cecb2b.com
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