Chapter 10:GTX-to-Board Interface
Table 10-9:Use Case 4 (Cont’d)
Connect To
GNDMGTAVTTRX(1)
GNDVCCINT
MGTAVTTTX with resistor(2)
Filter-Y---
Pin or Pin PairMGTAVTTRXMGTAVTTRXCMGTAVCCPLLMGTAVCCMGTRREF
Notes:
1.Connect to MGTAVTTRX of a used GTX_DUAL tile. Refer to Figure10-3, page257.
2.Connect to MGTAVTTTX of a used GTX_DUAL tile. Refer to Figure10-1, page256 and Figure10-4,page258.
Table10-10 shows the configuration for Use Case 5, where: •••
A GTX_DUAL tile is used only for forwarding resistor calibration informationgenerated in the center tile of the column and for forwarding a reference clockBoth transceivers are unusedBoundary-Scan is always functional
Use Case 5
Connect To
GND
Floating, no connectionFloating, no connection1.2V dedicated supply(1)
GNDMGTAVTTRX(2)
GNDVCCINT
MGTAVTTTX with resistor(3)
Filter---Y-Y---Pin or Pin PairMGTRXP/MGTRXNMGTTXP/MGTTXNMGTREFCLKP/MGTREFCLKN
MGTAVTTTXMGTAVTTRXMGTAVTTRXCMGTAVCCPLLMGTAVCCMGTRREF
Notes:
1.Refer to Figure10-5, page262.
2.Connect to MGTAVTTRX of a used GTX_DUAL tile. Refer to Figure10-3, page257.
3.Connect to MGTAVTTTX of a used GTX_DUAL tile. Refer to Figure10-1, page256 and Figure10-4,page258.
Table 10-10:
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
SelectIO to GTX Crosstalk Guidelines
Table 10-22:MGT132(1)MGT128(2)MGT124MGT120MGT116MGT112MGT114MGT118MGT122MGT126MGT130(2)MGT134(1)
Notes:
SelectIO Net Adjacent to Analog Supplies (FF1738 Packages)
1mmE15E9E5
F5, H5
N5W5AE5AL5AV5AV10AV16
P5, R4V5AD5, AF5, AG4AK5, AN4AT5, AV5AV6
AV9, AV11, AW12AV15, AW181.4mmE14, D13E10, E8, D7
GTX_DUAL Tile
1.The GTX_DUAL tile is only available on XC5VFX200T devices.
2.The GTX_DUAL tile is available on XC5VFX200T and XC5VFX130T devices.
Table 10-23:SelectIO Net Adjacent to MGTCLK (FF1738 Packages)
1mmD18, D13E10, D12, D7
F5K4, R4V5, T4AD5, AG4AK5, AH4, AN4
AT5AV9, AW7, AW12AV15, AW13, AW18,
AY19
1.4mmE17, E15, D12E9, D13D7E5, K4L5, N5, T4W5, R4AC5, AE5, AH4AJ5, AL5, AG4AR5, AN4AV5, AW7AV8, AV10, AW13AV14, AV16, AW12, BA19
GTX_DUAL Tile132_REFCLK(1)128_REFCLK(2)124_REFCLK120_REFCLK116_REFCLK112_REFCLK114_REFCLK118_REFCLK122_REFCLK126_REFCLK130_REFCLK(2)134_REFCLK(1)
Notes:
1.The GTX_DUAL tile is only available on XC5VFX200T devices.
2.The GTX_DUAL tile is available on XC5VFX200T and XC5VFX130T devices.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 10:GTX-to-Board Interface
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Section 2: Board Level Design
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 13:Design of Transitions
P/N Crossover Vias
Some transceivers offer the ability to independently switch the polarity of the transmit and receive signal pairs. This functionality eliminates the need to cross over the P/N signals at the board level, which in turn significantly enhances signal integrity. If possible, P/N crossover vias are to be avoided and the polarity switch of the transceiver should be used.
SMA Connectors
Well-designed SMA connectors can reduce debugging time and allow a high-performance channel to be designed correctly on the first pass. SMA connectors that perform well at 10Gb/s need to be simulated, designed, and manufactured to meet this performance target. Vendors can also offer design services that ensure that the connector works well on a specific board. Assembly guidelines are crucial in ensuring that the process of mating the connector to the board is well-controlled to give the specified performance.
Xilinx uses Rosenberger SMA connectors almost exclusively because of their excellent performance and because of the points listed in the previous paragraph.
Backplane Connectors
There are numerous signal integrity issues associated with backplane connectors including:•••
P/N signal skewCrosstalk
Stubs due to connector pins
Chapter14, “Guidelines and Examples,” provides a design example based on the popular HM-Zd connector.
Some connector manufacturers offer not only S parameters, models, and layout guidelines for their connectors but also design support, seminars, and tutorials.
Microstrip/Stripline Bends
A bend in a PCB trace is a transition. When routing differential traces through a 90° corner, the outer trace is longer than the inner trace, which introduces P/N imbalance. Even within a single trace, signal current has the tendency to hug the inside track of a corner, further reducing the actual delay through a bend.
To minimize skew between the P and N paths, 90° turns in microstrips or striplines are routed as two 45° bends to give mitered corners. The addition of a jog-out also allows the trace lengths to be matched. Figure13-16 shows example bends in traces.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009