EDA课设 实验报告数字时钟

1 具有时，分秒，计数显示功能，以24小时循环计时。 2 具有清零，调节小时，分钟功能。 3 具有整点报时功能。

实验目的

1掌握多位计数器相连的设计方法。

2 掌握十进制，六进制。二十四进制计数器的设计方法。 3 巩固多位共阴极扫描显示数码管的驱动及编码。 4 掌握扬声器的驱动。

5 掌握EDA技术的层次化设计方法。

顶层文件 数字时钟各模块连接图

程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; ENTITY SZZ IS

PORT (CLK,RESET,SETMIN,SETHOUR,CLKDSP:IN STD_LOGIC; SPEAKER:OUT STD_LOGIC;

LAMP:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); A,B,C,D,E,F,G,DPOUT:OUT STD_LOGIC); END SZZ;

ARCHITECTURE ONE OF SZZ IS COMPONENT SECOND

PORT(CLK,RESET,SETMIN:IN STD_LOGIC;

DAOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);

ENMIN:OUT STD_LOGIC); END COMPONENT; COMPONENT MINUTE

PORT(CLK,CLK1,RESET,SETHOUR:IN STD_LOGIC; ENHOUR:OUT STD_LOGIC;

DAOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END COMPONENT; COMPONENT HOUR

PORT(CLK,RESET:IN STD_LOGIC;

DAOUT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); END COMPONENT; COMPONENT ALERT

PORT(CLK:IN STD_LOGIC;

DAIN:IN STD_LOGIC_VECTOR(6 DOWNTO 0); LAMP:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); SPEAK:OUT STD_LOGIC); END COMPONENT; COMPONENT SELTIME

PORT(CLK1,RESET:IN STD_LOGIC;

SEC,MIN:IN STD_LOGIC_VECTOR(6 DOWNTO 0); HOUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0); DP:OUT STD_LOGIC;

DAOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END COMPONENT; COMPONENT DELED PORT(

NUM:IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END COMPONENT;

SIGNAL ENMIN_RE,ENHOUR_RE:STD_LOGIC;

SIGNAL SECOND_DAOUT,MINUTE_DAOUT:STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL HOUR_DAOUT:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL SELTIME_DAOUT:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL LEDOUT:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN

A<=LEDOUT(6);B<=LEDOUT(5);C<=LEDOUT(4);D<=LEDOUT(3); E<=LEDOUT(2);F<=LEDOUT(1);G<=LEDOUT(0); U1:SECOND PORT MAP (RESET=>RESET, CLK=>CLK,

SETMIN=>SETMIN, ENMIN=>ENMIN_RE,

DAOUT=>SECOND_DAOUT); U2:MINUTE PORT MAP (CLK=>ENMIN_RE,

CLK1=>CLK, RESET=>RESET, SETHOUR=>SETHOUR,

ENHOUR=>ENHOUR_RE, DAOUT=>MINUTE_DAOUT); U3:HOUR PORT MAP ( CLK=>ENHOUR_RE, RESET=>RESET,

DAOUT=>HOUR_DAOUT); U4:ALERT PORT MAP ( CLK=>CLK,

DAIN=>MINUTE_DAOUT, SPEAK=>SPEAKER, LAMP=>LAMP); U5:SELTIME PORT MAP (CLK1=>CLKDSP, RESET=>RESET,

SEC=>SECOND_DAOUT, MIN=>MINUTE_DAOUT, HOUR=>HOUR_DAOUT, DAOUT=>SELTIME_DAOUT, DP=>DPOUT, SEL=>SEL);

U6:DELED PORT MAP (NUM=>SELTIME_DAOUT, LED=>LEDOUT); END ONE;

仿真图

2 秒计数器 程序

library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all; entity second is port(

clk,reset,setmin:in std_logic; enmin :out std_logic;

daout:out std_logic_vector(6 downto 0)); end entity second;

architecture fun of second is

signal count:std_logic_vector(6 downto 0); signal enmin_1,enmin_2:std_logic; begin

daout<=count;

enmin_2<=(setmin and clk); enmin<=(enmin_1 or enmin_2); process(clk,reset,setmin) begin

if(reset='0')then count<=\"0000000\";

elsif(clk'event and clk='1')then if(count(3 downto 0)=\"1001\")then if(count<16#60#)then if(count=\"1011001\")then

enmin_1<='1';count<=\"0000000\"; else

count<=count+7; end if; else

count<=\"0000000\"; end if;

elsif(count<16#60#)then count<=count+1;

enmin_1<='0'after 100 ns; else

count<=\"0000000\"; end if; end if;

end process; end fun;

仿真图

3.分计时器

程序

LIBRARY ieee;

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all; ENTITY minute IS PORT(

clk,clk1,reset,sethour:IN STD_LOGIC; enhour:OUT STD_LOGIC;

daout:out std_logic_vector(6 downto 0)); END ENTITY minute;

ARCHITECTURE fun OF minute Is

SIGNAL count:STD_LOGIC_VECTOR(6 downto 0); SIGNAL enhour_1,enhour_2:STD_LOGIC; BEGIN daout<=count;

enhour_2<=(sethour and clk1); enhour<=(enhour_1 or enhour_2); process(clk,reset,sethour) begin

if(reset='0')then

count<=\"0000000\";

elsif(clk'event and clk='1')then

if(count(3 downto 0)=\"1001\")then if(count<16#60#)then

if(count=\"1011001\")then enhour_1<='1'; count<=\"0000000\"; ELSE

count<=count+7; end if; else

count<=\"0000000\"; end if;

elsif(count<16#60#)then count<=count+1;

enhour_1<='0'after 100 ns; else

count<=\"0000000\"; end if; end if; end process; END fun;

仿真图

4 小时文本 程序

library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all; entity hour is port(

clk,reset:in std_logic;

daout: out std_logic_vector(5 downto 0)); end hour;

architecture fun of hour is

signal count:std_logic_vector(5 downto 0); begin

daout<=count; process(clk,reset) begin

if(reset='0')then count<=\"000000\";

elsif(clk'event and clk='1')then

if(count(3 downto 0)=\"1001\")then if(count<16#23#)then

count<=count+7; else

count<=\"000000\"; end if;

elsif(count<16#23#)then count<=count+1; else

count<=\"000000\"; end if; end if;

end process; end fun;

仿真图

5 报警文本 程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ALERT IS PORT(

CLK:IN STD_LOGIC;

DAIN:IN STD_LOGIC_VECTOR(6 DOWNTO 0); SPEAK:OUT STD_LOGIC;

LAMP:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END ALERT;

ARCHITECTURE FIVE OF ALERT IS

SIGNAL COUNT:STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL COUNT1:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN

SPEAKER:PROCESS(CLK) BEGIN

SPEAK<=COUNT1(1);

IF(CLK'EVENT AND CLK='1') THEN IF(DAIN=\"0000000\") THEN IF(COUNT1>=\"10\") THEN COUNT1<=\"00\"; ELSE

COUNT1<=COUNT1+1; END IF; END IF; END IF;

END PROCESS SPEAKER; LAMPER:PROCESS(CLK) BEGIN

IF(RISING_EDGE(CLK)) THEN IF(COUNT<=\"10\") THEN IF(COUNT<=\"00\") THEN LAMP<=\"001\";

ELSIF(COUNT<=\"01\") THEN LAMP<=\"010\";

ELSIF(COUNT<=\"10\") THEN LAMP<=\"100\"; END IF;

COUNT<=COUNT+1; ELSE

COUNT<=\"00\"; END IF; END IF;

END PROCESS LAMPER; END FIVE;

仿真图

6 时间数据扫描分时选择模块文本 程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY SELTIME IS PORT(

CLK1,RESET:IN STD_LOGIC;

SEC,MIN:IN STD_LOGIC_VECTOR(6 DOWNTO 0); HOUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0); DAOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DP:OUT STD_LOGIC;

SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END SELTIME;

ARCHITECTURE SIX OF SELTIME IS

SIGNAL COUNT:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN

SEL<=COUNT;

PROCESS(CLK1,RESET) BEGIN

IF(RESET='0') THEN

COUNT<=\"000\";

ELSIF (CLK1'EVENT AND CLK1='1') THEN IF(COUNT>=\"101\") THEN COUNT<=\"000\"; ELSE

COUNT<=COUNT+1; END IF; END IF; CASE COUNT IS

WHEN \"000\"=>DAOUT<=SEC(3 DOWNTO 0); DP<='0'; WHEN \"001\"=>DAOUT(3)<='0';

DAOUT(2 DOWNTO 0)<=SEC(6 DOWNTO 4); DP<='0';

WHEN \"010\"=>DAOUT<=MIN(3 DOWNTO 0); DP<='1'; WHEN \"011\"=>DAOUT(3)<='0';

DAOUT(2 DOWNTO 0)<=MIN(6 DOWNTO 4); DP<='0';

WHEN \"100\"=>DAOUT<=HOUR(3 DOWNTO 0); DP<='1'; WHEN OTHERS=>DAOUT(3 DOWNTO 2)<=\"00\"; DAOUT(1 DOWNTO 0)<=HOUR(5 DOWNTO 4); DP<='0'; END CASE; END PROCESS;

END SIX;

仿真图

7 译码器文本 程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DELED IS

PORT (NUM:IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END DELED;

ARCHITECTURE SEVEN OF DELED IS BEGIN

LED<=\"1111110\"WHEN NUM=\"0000\"ELSE \"0110000\"WHEN NUM=\"0001\"ELSE \"1101101\"WHEN NUM=\"0010\"ELSE \"1111001\"WHEN NUM=\"0011\"ELSE \"0110011\"WHEN NUM=\"0100\"ELSE \"1011011\"WHEN NUM=\"0101\"ELSE \"1011111\"WHEN NUM=\"0110\"ELSE \"1110000\"WHEN NUM=\"0111\"ELSE

\"1111111\"WHEN NUM=\"1000\"ELSE \"1111011\"WHEN NUM=\"1001\"ELSE \"1110111\"WHEN NUM=\"1010\"ELSE \"0011111\"WHEN NUM=\"1011\"ELSE \"1001110\"WHEN NUM=\"1100\"ELSE \"0111101\"WHEN NUM=\"1101\"ELSE \"1001111\"WHEN NUM=\"1110\"ELSE \"1000111\"WHEN NUM=\"1111\"; END SEVEN;

仿真图

设计中遇到的问题与体会

在置数方面第一次写时在时钟沿内同步置数下载在试验箱上很难实现于是把置数改成异步置数。在报时模块一直没搞清需要达到怎样的报时效果所以花费时间最长。 在设计数字时钟时通过解决在编程调试以及仿真过程中出现的种种问题加深了我们对软件设计坏境的熟悉程度。令我印象最深的就是在编程中虽然有些程序的结构获得的效果以及软件仿真的结果是一致的但在实际硬件实现却会有很大的不同。通过设计我们更深的认识了EDA技术受益匪浅。